Design of ALU using reversible logic based Low Power Vedic Multiplier
نویسنده
چکیده
Arithmetic Logic Unit (ALU) is a heart of microprocessor and microcontroller units that are playing main role in digital computers. By optimizing the ALU circuit in microprocessor and microcontroller highly power efficient digital system can be achieved. The use of low power and high performance sub-blocks like adder and multiplier can reduce the total power dissipation of ALU. So in this paper we are introducing new architecture for a high speed and area efficient Vedic multiplier and an adder circuit using reversible logic gates. The proposed adder and multipliers are employed in the implementation of Arithmetic Logic Unit (ALU) to reduce the power dissipation and area and to improve the performance sufficiently. Integration of low power sub-blocks of ALU resulted that the power dissipation of proposed ALU unit is reduced when compared with the conventional unit. The proposed logic blocks are implemented using Verilog HDL programming language, simulated and synthesized using Xilinx ISE 9.2i software.
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